The present invention relates to bus driver circuitry and more particularly to driving high speed data lines with compensation for process voltage temperature effects.
A PCI bus system typically interconnects a large number of electronic devices. The system must maintain, manage and communicate bi-directional data from one device to another device or several devices at once. Each device may output different voltage levels while maintaining capability to read data on the bus. One reason for the difficulty of continuously increasing bus speeds to match the continuously increasing processor speeds is that input/output buffers coupled to the busses must often operate across a wide variety of operating conditions. For instance, the performance of an input/output buffer changes with respect to conditions such as process, voltage and temperature.
A parallel data bus typically comprises a number of bus lines to which the components of a computer system may be connected for communicating information between one another. Each component coupled to the data bus typically includes a set of bus driver circuits for transmitting data via the bus lines by switching the voltages of the bus lines between voltages that correspond to logic states, however defined. The speed at which a bus driver circuit switches the voltages of the bus line between logic states is called the xe2x80x9cslew rate,xe2x80x9d and the slew rate of the bus driver circuit is an extremely important characteristic for ensuring proper operation of the bus driver circuit at the clock speed of the data bus.
FIG. 1 shows a simplified sketch of a prior art PCI-X driver utilizing the feature of controlled output impedance. The input signal is routed by a number of gates to appropriate driver""s output devices. The device selection is determined by impedance controller to correct for Process/Voltage/Temperature (PVT) effects. The size of these devices (MP1x, MP2x, . . . MP1x) are weighted in a certain manner (binary or with other ratios) to achieve a desired output impedance in conjunction with discrete resistor Rp or RN. Control signals for selection of a specific device are labeled CTRL and are generated by impedance controller as static logic signal and are set periodically to make the PVT adjustments to the output impedance.
P-channel and N-channel output devices are selected by separate paths to allow enabling the particular device, dual power supply mode of operation and also for the power-down feature.
To select the output device MP1x, the control signal CTRL1P is set low and CTRL2P is set high. This selection with channel the input signal IN through inverters I1, I2, NOR gate N1 and AND gate A1 to the gate of device MP1x. The MP1x device provides drive for positive-going or rising output signal.
Similarly, for the falling edge of the output signal, MN1x is selected by setting CTRL1N high, CTRL2N, low and CTRL3N also low. In the case, the input signal IN is channeled to the gate of N-channel MOSFET MN1x output device through inverters I1, I2, NAND gate N2, and NOR gates N2 and N3.
The greatest shortcoming of this approach is the excessive propagation delay from input IN to the output OUT due to the number of stages that the input signal has to propagate. In this case, there are five stages of delays, although in other implementations there may be a greater number of stages for more sophisticated PVT controllers. Since logical components of the same kind have variances in their individual propagation times from input to output, the greater the number of stages, the greater the potential cumulative variances of the propagation time of the various output drivers of the bus.
Another problem is adequately controlling the rise and fall times in complex output buffers. Large output devices are required for the delivery of adequate signal to drive transmission lines such as back-plane printed circuit board traces. As a result, the output impedances of the buffers become much lower than the characteristic impedances of the drive transmission lines. Consequently, mismatches lead to signal reflections and ringing and negatively affect the signal integrity. Recent drivers offer controlled output impedances to minimize the impedance mismatches.
Yet another problem results from the circuit implementation of FIG. 1 is a lack of output signal slew rate control. The output signal transition may be too fast or too slow depending upon device sizes, the circuit parasitics, PVT conditions, and buffer load.
One disadvantage of operating a system at a high speed is that the system may not provide a desired slew rate at high operating speeds. In particular, the constraints on loading, bus length, and bus pitch in conjunction with block data transfer do not provide for a stable slew rate at several hundred MHz or higher.
Another disadvantage of operating the system at high speed is that the system incurs ringing in the power lines VDD and GND, resulting in signal distortion. Thus, the inductive/capacitive characteristics of the bus and signal lines are exaggerated at a higher frequency resulting in signal distortion.
Yet another disadvantage of operating the system at high speed is that the system cannot provide low error rates. In particular, at high operating frequencies, the clocking scheme of the system does not guarantee synchronization between transmitted data and the clocking scheme in the destination device. Thus, incorrect data can be captured in a destination device.
The prior art approaches exhibit unacceptable signal delays and uncontrolled output signal rise and fall times.
The prior art drive circuits do not meet the newer high speed driver requirements for interface communications.
In the prior art, the slew rate was asymmetric.
This invention presents a method and device for driving high speed data lines by reducing the number of logic stages, separating the control logic from the data logic, and controlling a variable impedance circuit according to process, voltage, temperature (PVT) variations.
This invention relates to a circuit comprising a driver circuit configured to output a signal; a first capacitance formed from a portion of the driver circuit from a combination of discrete and parasitic capacitances; and a variable impedance circuit forming a portion of the driver circuit and coupled to the first capacitance, the variable impedance circuit configured to adjust the slew rate in response to changes in fabrication process and operating conditions wherein the variable impedance circuit comprises a first resistor, a first NMOS transistor and a first PMOS transistor in parallel and coupled to the first capacitance, wherein the gate of the first PMOS transistor is coupled to a process, voltage, and temperature controller.
This invention relates to a variable impedance circuit for use in a bus driver circuit, comprising a first impedance, a first NMOS transistor and a first PMOS transistor in parallel, a second impedance, a second NMOS transistor and a second PMOS transistor in parallel, wherein the a first combination of the first impedance, the first NMOS transistor, and the first PMOS transistor have a first end and an opposing second end and the second combination of the second impedance, the second NMOS transistor, and the second PMOS transistor has a third end and a fourth end, wherein the second end of the first combination and the third end of the second combination are directly electrically connected, wherein the first end of the first combination receives an input signal.
This invention relates to a bus driver circuit, comprising a first CMOS inverter which includes a first PMOS transistor and a first NMOS transistor, the transistors being electrically connected to one another; a first set of logic gates for controlling the first PMOS transistor by a first control signal; a second set of logic gates for passing an first input signal; and a third set of logic gates for controlling the first NMOS transistor by a second control signal; wherein the first set of logic gates, the second set of logic gates, and the third set of logic gates have no logic gates in common.
This invention relates to a method of outputting a signal on a bus driver circuit, comprising inputting an initial input signal; providing process, voltage, temperature controller signals to a variable impedance circuit through which at least a portion of the initial input signal passes; and outputting an output signal corresponding to the initial input signal.
This invention relates to a method of outputting a signal on a bus driver circuit, comprising providing separate logic paths for the control signals and the data signal.
This invention improves the bus driver circuit""s propagation delay and controls the output signal rise and fall times by using a lower number of logic stages.
This invention provides better performance over current devices.
This invention offers cost effectiveness as the circuitry requires a reduced silicon area.